(1) Field of the Invention
The invention relates to electronic circuit design. More specifically, the invention relates to a variable delay cell with self-biasing load for use in obtaining a differential output signal.
(2) Related Art
For purposes of noise reduction it is often desirable to use differential rather than a single-ended signaling. For a gain device such as an op amp using a differential pair since high gain is desired, a high impedance load is necessary. Additionally, the load must be chosen such that the voltage drop across the load transistors of the differential pair is not so high that the differential pair goes into the triode region of operation. This has typically been accomplished using current sources as the loads on each leg of the differential pair. For example, a transistor with a suitable externally generated bias current applied to its gate so that the transistor remains in saturation acts as an approximately constant current source. Thus, two transistors with their gates appropriately biased, source current and provide a high impedance load. However, the generation of the bias current applied to the gates must be very accurate to keep the load transistors and differential pair transistors in saturation.
FIG. 1 is a schematic diagram of a prior art variable delay cell. A differential pair 1 receives a differential input voltage at its gates. A second differential pair 2 receives a differential control signal at its gates. One of the transistors of differential pair 2 has its drain coupled to the sources of the first differential pair. The second transistor of differential pair 2 has its drain coupled to the sources of a pair of cross-coupled transistors which in turn are coupled to the drains of the first differential pair 1. Biasing transistor 4 is driven by an externally supplied NBIAS voltage and controls the amount of current drawn through the second differential pair 2. A second biasing transistor 3 is coupled to the sources of the first differential pair 1 and ensures that the transistors of the first differential pair 1 remain in the saturation region. The first differential pair 1 is loaded by a pair of diode-connected transistors 6 and a variable resistance created by the cross-coupled transistors 5. This embodiment varies the effective resistance seen by the first differential pair 1 through the use of positive feedback. Thus, current is varied between the amplifier and the cross-coupled transistors 5 to maintain a constant output swing. Unfortunately, using this approach, the differential control voltages are not symmetrical. Specifically, an increase in voltage on one control node will not adjust the frequency the same as a decrease in voltage on the other control node. This results in a non-linear gain curve for a voltage controlled oscillator (VCO) using these cells. One of ordinary skill in the art will recognize that linearity of the gain curve is very important in VCOs. Particularly, the linearity of the gain curve is directly related to jitter in the output signal of the VCO.
FIG. 2 is a schematic and block diagram of another prior art delay cell. A voltage to current converter 30 is used to create a control bias current (IBIAS) from an applied control voltage. This bias current is mirrored into the VCO stages through the use of the control voltage CTLBIAS. Voltage to current converter 30 employs a differential pair 31 biased by a biasing transistor 33 with an external NBIAS current applied to its gate. The differential pair 31 has differential control signal applied to its gates. Mirroring transistor 35 mirrors the current drawn through diode connected transistor 37. Transistor 36 is coupled to complete the configuration. This mirrored current IBIAS provides the biasing current for a delay stage 140. Unfortunately, the converter 30 introduces delay into the phase lock loop feedback loop from when the voltage changes to when the frequency changes. This has a negative effect on jitter and decreases the stability of the phase lock loop.
In delay stage 140 a differential pair 12 receives a differential input, IN and INZ. The differential pair 12 is coupled to a biasing transistor 13 which is governed by the bias voltage, CTLBIAS. The biasing transistor 13 acts as a current source pulling a current I through the differential pair to ground. Four transistors form the load 10. One diode connected transistor 21 and one non-diode connected transistor 11 is coupled along each leg of the differential pair 12. The impedance of load 10 dictates the amount of gain present at output nodes 14. The bias voltage LOADBIAS must be provided to the gate of non-diode connected transistors 11 such that transistors 11 remain in saturation at the switching point. The sum of the currents sourced through load 10 must equal I or at least one of the transistors will leave the saturation region. Because CTLBIAS is set so that transistor 13 is in saturation and delivering a current I, the two sides of the load must deliver I/2 at the switching point. If LOADBIAS is not precisely set, the two sides may source too much or too little current. As a result one or more of the transistors of the load or the differential pair will be forced out of saturation.
To ensure that the transistors of the delay stage remain in saturation a special circuit is required to insure that the load is correctly biased. In FIG. 2, to generate LOADBIAS, a bias generating circuit 150 is coupled to the gates of transistors 11 of the load 10. Bias generating circuit 150 is a differential amplifier with all transistors except the current source diode connected. The transistors are selected so that LOADBIAS will maintain the load in saturation for expected values of CTLBIAS. Higher speed signaling in the range of one to two gigahertz coupled with the tight jitter requirements of existing serial protocols makes it extraordinarily difficult to properly control CTLBIAS and LOADBIAS to satisfy these requirements. Specifically, this implementation is slow settling due to the delay in the voltage to current stage 30 and the delay in the biasing stage 150.
In view of the foregoing, it would be desirable to have a variable delay cell with symmetrical control voltage response and good jitter characteristics. It would also be desirable to be able to accomplish this with a highly flexible design that minimizes the delay in the PLL feedback loop by reacting quickly to a change in the control voltage (CTL and CTLZ) and is easily and cost-effectively implemented.